Search - vhdl pwm

[VHDL-FPGA-Verilog] 自定义逻辑PWM的例子

Description: 是一个用vhdl语言编写的pwm程序，可以方便地用来和nios连接，实现对nios的功能扩展。-is a VHDL language with the PWM procedures can be used to facilitate connections and nios, nios to achieve a functional extension.
Platform: | Size: 10240 | Author: 石坚 | Hits:

[VHDL-FPGA-Verilog] VHDL 的实例程序，共44个

Description: 经典VHDL 的实例程序，共44个！要下载的尽快-classic examples of VHDL, with a total of 44! To download as soon as possible
Platform: | Size: 43008 | Author: 立立 | Hits:

[VHDL-FPGA-Verilog] NIOS PWM inc

Description: NIOS环境PWM的USER LOGIC实例5-NIOS environment PWM USER Logic Case 5
Platform: | Size: 1024 | Author: 黄建生 | Hits:

[VHDL-FPGA-Verilog] PWM

Description: done pwm control using vhdl ,you can look at it.
Platform: | Size: 2048 | Author: fff | Hits:

[assembly language] PWM

Description: 利用汇编语言编写,VHDL,实现PWM波形转换电压,直接导入单片机即可运行,产生波形输出实现转换电压的功能.-Prepared to use assembly language, VHDL, realize PWM waveform converter voltage, can be run directly into single-chip, resulting in the output waveform realize the function of voltage conversion.
Platform: | Size: 1064960 | Author: yangfan | Hits:

[VHDL-FPGA-Verilog] newlin-pwm

Description: VHDL 源码模块，可以实现最经典原PWM，可以用于电源，电机的控制
Platform: | Size: 1024 | Author: 骑士 | Hits:

[VHDL-FPGA-Verilog] PWM

Description: 利用VHDL语言实现FPGA的PWM输出波形，占空比可控-FPGA using VHDL language realize the PWM output waveform, duty cycle controlled
Platform: | Size: 36864 | Author: 王传辉 | Hits:

[VHDL-FPGA-Verilog] pwm

Description: 在SPARTAN 3E开发平台上，利用其板子上一些I/O口或LED来实现PWM的设计上传文件中pwm_ctrl是用picoblaze实现的PWM控制文件，另外一个则是在ISE设计中的顶层文件。-SPARTAN 3E in the development platform, the use of its board of some I/O port or LED to achieve the design of PWM upload is pwm_ctrl PicoBlaze realize the PWM control file, another is in the top-level ISE design files.
Platform: | Size: 6144 | Author: 张杰 | Hits:

[VHDL-FPGA-Verilog] cpld-pwm

Description: 基于cpld的pwm控制设计采用vhdl.verilog语言设计对大家比较有用-CPLD-based control design uses the pwm design vhdl.verilog language more useful for everyone
Platform: | Size: 79872 | Author: emily | Hits:

[SCM] pwm

Description: 一个PWM波的设计实例。弄直流点击的可以认真的学习一下，或许可以受到启发。-A PWM wave design example. DC clicks can get serious about learning, may be able to be inspired.
Platform: | Size: 1024 | Author: chengpan | Hits:

[SCM] PWM

Description: 用VKDL语言编写的PWM控制程序很有用本例只做了5路PWM-VKDL languages with PWM control procedures useful in this case only a 5 PWM
Platform: | Size: 394240 | Author: xhb | Hits:

[Other] pwm

Description: 通过改变pwm的占空比，调节LED灯的亮暗程度-By changing the duty cycle pwm, regulating bright LED lights concealed the extent of
Platform: | Size: 209920 | Author: liupeinan | Hits:

[VHDL-FPGA-Verilog] PWM

Description: 脉冲宽度调制，VHDL代码编写，包括QUARTUSII和MODELSIM工程以及testbench-Pulse width modulation, VHDL coding, including QUARTUSII and ModelSim engineering and Testbench
Platform: | Size: 348160 | Author: horse | Hits:

[VHDL-FPGA-Verilog] pwm

Description: 实现PWM波型....使用VHDL语言-Realization of PWM waveform using the VHDL language ....
Platform: | Size: 370688 | Author: xxj | Hits:

[VHDL-FPGA-Verilog] pwm-c

Description: 用VHDL编写的PWM控制程序，通过寄存器控制20余路PWM输出；qar是quartus的压缩包格式-VHDL prepared using PWM control procedures, through the registers to control more than 20 road PWM output qar is Quartus compressed packet format
Platform: | Size: 119808 | Author: mu | Hits:

[VHDL-FPGA-Verilog] PWM

Description: 使用VERILOG 语言产生PWM波。只需要使用处理器或内核直接配置相应的寄存器就可以输出PWM波。-VERILOG language use PWM wave generated. Only need to use the processor or core directly corresponding configuration register can output PWM wave.
Platform: | Size: 2048 | Author: 望习才 | Hits:

[SCM] PWM

Description: 实现三相pwm控制，从而控制三相逆变器的变化速度-The realization of three-phase pwm control, three-phase inverter to control the pace of change
Platform: | Size: 1024 | Author: rocky | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: PWM控制就是产生一定周期，占空比不同的方波信号，当占空比较大时，电机转速较高，否则电机转速较低。当采用FPGA产生PWM波形时，只需FPGA内部资源就可以实现，数字比较器的一端接设定值输出，另一端接线性递增计数器输出。当线性计数器的计数值小于设定值时输出低电平，当计数器大于设定值时输出高电平，这样就可通过改变设定值，产生占空比不同的方波信号，从而达到控制直流电机转速的目的。直流电机控制电路主要由2部分组成，如图1所示：  FPGA中PWM脉宽调制信号产生电路；  FPGA中正/反转方向控制电路 -PWM control is a certain cycle, a different duty cycle square wave signal, when the duty cycle is high, higher motor speed, or lower motor speed. When the PWM waveform generated using FPGA, the FPGA internal resources only can be achieved, the figure one comparator output termination setting, the other linear incremental counter output termination. When the value of linear counter output is less than low-level settings, when the counter output is greater than high settings, so that by changing the settings can produce different duty cycle square wave signal, DC motor control to achieve the purpose of speed. DC motor control circuit mainly by 2 parts, as shown in Figure 1:  FPGA in the PWM pulse width modulation signal generator circuit Chiang Kai-shek  FPGA/reverse direction control circuit
Platform: | Size: 37888 | Author: 袁玉佳 | Hits:

[VHDL-FPGA-Verilog] pwm

Description: 用硬件描述语言实现脉宽调制 VHDL 例子-PWM through VHDL
Platform: | Size: 1024 | Author: Wayne Gao | Hits:

[VHDL-FPGA-Verilog] PWM

Description: 实现PWM波的产生,可用于电机控制.可以改变其占空比及频率来实现电机的调速.-Realization of PWM wave generation, can be used for motor control. Can change its duty cycle and frequency to achieve the speed control motor.
Platform: | Size: 436224 | Author: 宋瑞鹏 | Hits:

« 12 3 4 5 6 7 8 9 10 »

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[VHDL-FPGA-Verilog] 自定义逻辑PWM的例子

[VHDL-FPGA-Verilog] VHDL 的实例程序，共44个

[VHDL-FPGA-Verilog] NIOS PWM inc

[VHDL-FPGA-Verilog] PWM

[assembly language] PWM

[VHDL-FPGA-Verilog] newlin-pwm

[VHDL-FPGA-Verilog] PWM

[VHDL-FPGA-Verilog] pwm

[VHDL-FPGA-Verilog] cpld-pwm

[SCM] pwm

[SCM] PWM

[Other] pwm

[VHDL-FPGA-Verilog] PWM

[VHDL-FPGA-Verilog] pwm

[VHDL-FPGA-Verilog] pwm-c

[VHDL-FPGA-Verilog] PWM

[SCM] PWM

[VHDL-FPGA-Verilog] VHDL

[VHDL-FPGA-Verilog] pwm

[VHDL-FPGA-Verilog] PWM

CodeBus www.codebus.net